The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device having a monitoring device capable of measuring the line delay or a model parameter of a wordline or a bitline.
As the integration density of a semiconductor memory device increases, the RC delay and a model parameter of a wordline or a bitline have a significant effect on a semiconductor memory device characteristic. The RC delay and the model parameter are important factors to accurately set timing in an internal operation and to determine whether the goods are commercially competitive. However, there are few methods capable of reliably measuring the RC delay and the model parameter. A method, which is currently in use to measure the line delay, is not a direct measurement, but an indirect measurement so that an accurate measurement cannot be performed.
FIG. 1 is a schematic circuit diagram showing a portion of cell block in a DRAM according to the prior art.
Referring to FIG. 1, a wordline driver WD is driven in response to a main wordline enable bar signal mwlz outputted from a row decoder (not shown) and a wordline boosting signal Px is applied to a wordline WLn connected to a memory cell 2 by the wordline driver WD. Generally, a dummy wordline and a dummy memory cell, which have the same width and area as the normal wordline and the normal memory cell, are configured at the edge of the normal wordline WLn for stability of a process.
The main wordline signal is selected by a row address and one normal wordline boosting signal Px is selected from Px0 to Px3 by the address signal and then a voltage level of the normal wordline WLn is changed into a boosting voltage Vpp level, which is higher than a power supply voltage level. One wordline WLn is driven to the boosting voltage Vpp level in response to the main wordline signal. At this time, the dummy wordline is not used so that the voltage level of the dummy wordline is fixed to a ground voltage level. Also, a dummy bitline voltage level is set to a Vblp level, which is a bitline precharge voltage level.
In the above configuration, after manufacturing real goods, a characteristic of the goods is determined by how rapidly the voltage level of the wordline WLn or the bitline BL increases to a desired voltage level. It is very important to determine whether the enable time of a bitline sense amplifier, a tRCD_min and a model parameter are matched with those of an actual device. However, an accurate measurement method has not been implemented in the prior art. A conventional measurement method is to measure a data line, which can be measured because the data line is a metal line, and indirectly guess the desired data, so that accurate data cannot be obtained.
It is, therefore, an object of the present invention to provide a semiconductor memory device having a monitoring circuit capable of measuring the line delay or a model parameter of a wordline or a bitline.
In accordance with an aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of dummy wordlines independently formed with a plurality of normal wordlines; a plurality of dummy wordline drivers for driving the plurality of dummy wordlines; a plurality of control circuits for controlling the plurality of dummy wordline drivers; a plurality of comparing means for comparing a voltage level of the dummy wordline and the predetermined reference voltage level; and a plurality of outputting means for outputting signals outputted from the plurality of comparing means.
In accordance with another aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of dummy bitlines independently formed with a plurality of normal bitlines; a plurality of dummy bitline drivers for driving the plurality of dummy bitlines; a plurality of control circuits for controlling the plurality of dummy bitline drivers; a plurality of comparing means for comparing a voltage level of the dummy bitline and the predetermined reference voltage level; and a plurality of outputting means for outputting signals outputted from the plurality of comparing means.
In accordance with a still further aspect of the present invention, there is provided a semiconductor memory device comprising; a plurality of dummy wordlines independently formed with a plurality of normal wordlines; a plurality of normal bitlines independently formed with a plurality of normal bitlines; a monitoring means for measuring voltage on the dummy bitline or the dummy wordline; and a control circuit for controlling the monitoring means.